Source: covered Section: electronics Priority: optional Maintainer: Debian Electronics Team Uploaders: أحمد المحمودي (Ahmed El-Mahmoudy) Build-Depends: debhelper-compat (= 13), flex, bison, gperf, tcl-dev, tk-dev, libxft2-dev, iverilog | verilog, gplcver (>= 2.12a-1.1) Standards-Version: 4.6.2 Rules-Requires-Root: no Homepage: http://covered.sourceforge.net/ Vcs-Git: https://salsa.debian.org/electronics-team/covered.git Vcs-Browser: https://salsa.debian.org/electronics-team/covered Package: covered Architecture: any Depends: ${shlibs:Depends}, ${misc:Depends}, tklib Recommends: iverilog | verilog | gplcver (>= 2.12a-1.1) Description: Verilog code coverage analysis tool Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage. Package: covered-doc Section: doc Architecture: all Depends: ${misc:Depends} Description: Verilog code coverage analysis tool - documentation Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage. . This package contains the documentation.